On Wednesday, at the Tencent Digital Ecosystem Summit, Tang Daosheng, Senior Executive Vice President of Tencent and President of the Cloud and Smart Industry Group, said Tencent has made a long-term plan in regard to chip R&D and investment for businesses that host large-scale operations and has achieved substantial progress in three main areas.
The three chips in progress refer to Zixiao for AI computing, Canghai for video processing and Xuanling for high-performance networks.
In the speech, Qiu Yuepeng, Vice President of Tencent, COO of Cloud and Smart Industry Group and President of Tencent Cloud, said that the performance of Tencent‘s AI reasoning chip Zixiao has improved by 100% compared with the industry standard and its compression rate is more than 30% higher than its competitors. The intelligent network card chip Xuanling has improved its performance than that of other products in the industry by four times, and could accelerate the performance for cloud networks.
“Chips are at the core of hardware and also the core infrastructure of the industrial Internet,” explained Tang Daosheng. He went on to say that Tencent will continue to actively explore and work on long-term investments, and seek to maintain deep strategic cooperation agreements with chip companies at home and abroad through ecological co-construction.
Tencent Cloud has launched its Xingxinghai Server jointly with many chip firms, and released China’s first cloud server product series for large-scale applications of 100G super networks, whose underlying hardware support is also the Xingxinghai Server. Over the past year, the scale of Xingxinghai went up by 400 times, making it the fastest growing server product in the industry.
Tencent has made inroads in its chip R&D. The company recently invested in Enflame Technology, a cloud AI chip enterprise, whichreleased its second generation AI chip slated to be mass-produced by the end of this year. Tencent also set up Penglai Lab in 2020 which is focusing on chip R&D. The company is aiming to achieveend-to-end coverage of chip design and verification.